MyHDL is a Python package for using Python as a hardware description language. Popular hardware description languages, like Verilog and VHDL, are compiled languages. MyHDL with Python can be viewed as a "scripting language" counterpart of such languages. However, Python is more accurately described as a very high level language (VHLL). MyHDL users have access to the amazing power and elegance of Python for their modeling work. This package is GPL Cver cosimulation support for py-MyHDL.
Binary packages can be installed with the high-level tool pkgin (which can be installed with pkg_add) or pkg_add(1) (installed by default). The NetBSD packages collection is also designed to permit easy installation from source.
The pkg_admin audit command locates any installed package which has been mentioned in security advisories as having vulnerabilities.
Please note the vulnerabilities database might not be fully accurate, and not every bug is exploitable with every configuration.
Problem reports, updates or suggestions for this package should be reported with send-pr.