# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		full_featured_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C25F324C8
#set_global_assignment -name TOP_LEVEL_ENTITY full_featured
#set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
#set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:54:53  MAY 22, 2006"
#set_global_assignment -name LAST_QUARTUS_VERSION "6.0 SP1"
#set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
#set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
#set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
#set_global_assignment -name BDF_FILE full_featured.bdf
#set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:auto_verify_ddr_timing.tcl"
#set_location_assignment PIN_V25 -to address[0]
set_global_assignment -name NUM_PARALLEL_PROCESSORS 2

set_location_assignment PIN_E12 -to address[1]
set_location_assignment PIN_A16 -to address[2]
set_location_assignment PIN_B16 -to address[3]
set_location_assignment PIN_A15 -to address[4]
set_location_assignment PIN_B15 -to address[5]
set_location_assignment PIN_A14 -to address[6]
set_location_assignment PIN_B14 -to address[7]
set_location_assignment PIN_A13 -to address[8]
set_location_assignment PIN_B13 -to address[9]
set_location_assignment PIN_A12 -to address[10]
set_location_assignment PIN_B12 -to address[11]
set_location_assignment PIN_A11 -to address[12]
set_location_assignment PIN_B11 -to address[13]
set_location_assignment PIN_C10 -to address[14]
set_location_assignment PIN_D10 -to address[15]
set_location_assignment PIN_E10 -to address[16]
set_location_assignment PIN_C9  -to address[17]
set_location_assignment PIN_D9  -to address[18]
set_location_assignment PIN_A7  -to address[19]
set_location_assignment PIN_A6  -to address[20]
set_location_assignment PIN_B18 -to address[21]
set_location_assignment PIN_C17 -to address[22]
set_location_assignment PIN_C18 -to address[23]
set_location_assignment PIN_G14 -to address[24]
set_location_assignment PIN_B17 -to address[25]
#big endian encoding of data bus
set_location_assignment PIN_C16 -to data[0] #flash_sramdq[16]
set_location_assignment PIN_D12 -to data[1] #flash_sramdq[17]
set_location_assignment PIN_E11 -to data[2] #flash_sramdq[18]
set_location_assignment PIN_D2  -to data[3] #flash_sramdq[19]
set_location_assignment PIN_E13 -to data[4] #flash_sramdq[20]
set_location_assignment PIN_E14 -to data[5] #flash_sramdq[21]
set_location_assignment PIN_A17 -to data[6] #flash_sramdq[22]
set_location_assignment PIN_D16 -to data[7] #flash_sramdq[23]
set_location_assignment PIN_C12 -to data[8] #flash_sramdq[24]
set_location_assignment PIN_A18 -to data[9] #flash_sramdq[25]
set_location_assignment PIN_F8  -to data[10] #flash_sramdq[26]
set_location_assignment PIN_D7  -to data[11] #flash_sramdq[27]
set_location_assignment PIN_F6  -to data[12] #flash_sramdq[28]
set_location_assignment PIN_E6  -to data[13] #flash_sramdq[29]
set_location_assignment PIN_G6  -to data[14] #flash_sramdq[30]
set_location_assignment PIN_C7  -to data[15] #flash_sramdq[31]
set_location_assignment PIN_H3  -to data[16] #flash_sramdq[0]
set_location_assignment PIN_D1  -to data[17] #flash_sramdq[1]
set_location_assignment PIN_A8  -to data[18] #flash_sramdq[2]
set_location_assignment PIN_B8  -to data[19] #flash_sramdq[3]
set_location_assignment PIN_B7  -to data[20] #flash_sramdq[4]
set_location_assignment PIN_C5  -to data[21] #flash_sramdq[5]
set_location_assignment PIN_E8  -to data[22] #flash_sramdq[6]
set_location_assignment PIN_A4  -to data[23] #flash_sramdq[7]
set_location_assignment PIN_B4  -to data[24] #flash_sramdq[8]
set_location_assignment PIN_E7  -to data[25] #flash_sramdq[9]
set_location_assignment PIN_A3  -to data[26] #flash_sramdq[10]
set_location_assignment PIN_B3  -to data[27] #flash_sramdq[11]
set_location_assignment PIN_D5  -to data[28] #flash_sramdq[12]
set_location_assignment PIN_B5  -to data[29] #flash_sramdq[13]
set_location_assignment PIN_A5  -to data[30] #flash_sramdq[14]
set_location_assignment PIN_B6  -to data[31] #flash_sramdq[15]
set_location_assignment PIN_H6   -to rxd1 #MSMC_D0
set_location_assignment PIN_D3   -to txd1 #MSMC_D1
set_location_assignment PIN_F1 -to gpio[0] #KEY0
set_location_assignment PIN_F2 -to gpio[1] #KEY1
set_location_assignment PIN_A10 -to gpio[2] #KEY2
set_location_assignment PIN_B10 -to dsubren #KEY3
set_location_assignment PIN_P13 -to dsuact  #LED0
set_location_assignment PIN_N12 -to errorn  #LED2
set_location_assignment PIN_D17 -to oen #flash_we_n
set_location_assignment PIN_E2  -to romsn #flash_ce_n
set_location_assignment PIN_D18 -to writen #flash_we_n
set_location_assignment PIN_C3  -to rstoutn #flash_reset_n

set_location_assignment PIN_F7  -to ssram_adscn #sram_adsc_n
set_location_assignment PIN_F10 -to ssram_bw[2] #sram_be_n[0]
set_location_assignment PIN_F11 -to ssram_bw[3] #sram_be_n[1]
set_location_assignment PIN_F12 -to ssram_bw[0] #sram_be_n[2]
set_location_assignment PIN_F13 -to ssram_bw[1] #sram_be_n[3]
set_location_assignment PIN_G13 -to ssram_wen #sram_we_n
set_location_assignment PIN_F9  -to ssram_cen #sram_ce1_n
set_location_assignment PIN_E9  -to ssram_oen #sram_oe_n
set_location_assignment PIN_A2  -to ssram_clk

set_location_assignment PIN_B9  -to clk #osc_clk1
set_location_assignment PIN_N2 -to resetn #pld_clear_n
set_location_assignment PIN_U2 -to ddr_clk #clk_to_sdram[0]
set_location_assignment PIN_V2 -to ddr_clkn #clk_to_sdram_n[0]
set_location_assignment PIN_U1 -to ddr_ad[0]
set_location_assignment PIN_U5 -to ddr_ad[1]
set_location_assignment PIN_U7 -to ddr_ad[2]
set_location_assignment PIN_U8 -to ddr_ad[3]
set_location_assignment PIN_P8 -to ddr_ad[4]
set_location_assignment PIN_P7  -to ddr_ad[5]
set_location_assignment PIN_P6  -to ddr_ad[6]
set_location_assignment PIN_T14 -to ddr_ad[7]
set_location_assignment PIN_T13 -to ddr_ad[8]
set_location_assignment PIN_V13 -to ddr_ad[9]
set_location_assignment PIN_U17 -to ddr_ad[10]
set_location_assignment PIN_V17 -to ddr_ad[11]
set_location_assignment PIN_U16 -to ddr_ad[12]
set_location_assignment PIN_V11 -to ddr_ba[0]
set_location_assignment PIN_V12 -to ddr_ba[1]
set_location_assignment PIN_T4 -to ddr_casb
set_location_assignment PIN_R13 -to ddr_cke
set_location_assignment PIN_V1  -to ddr_csb
set_location_assignment PIN_V16 -to ddr_rasb
set_location_assignment PIN_U15 -to ddr_web
set_location_assignment PIN_U4 -to ddr_dq[0]
set_location_assignment PIN_V4 -to ddr_dq[1]
set_location_assignment PIN_R8 -to ddr_dq[2]
set_location_assignment PIN_V5 -to ddr_dq[3]
set_location_assignment PIN_P9  -to ddr_dq[4]
set_location_assignment PIN_U6  -to ddr_dq[5]
set_location_assignment PIN_V6  -to ddr_dq[6]
set_location_assignment PIN_V7  -to ddr_dq[7]
set_location_assignment PIN_U13 -to ddr_dq[8]
set_location_assignment PIN_U12 -to ddr_dq[9]
set_location_assignment PIN_U11 -to ddr_dq[10]
set_location_assignment PIN_V15 -to ddr_dq[11]
set_location_assignment PIN_U14 -to ddr_dq[12]
set_location_assignment PIN_R11 -to ddr_dq[13]
set_location_assignment PIN_P10 -to ddr_dq[14]
set_location_assignment PIN_V14 -to ddr_dq[15]
set_location_assignment PIN_U3 -to ddr_dqs[0]
set_location_assignment PIN_T8 -to ddr_dqs[1]
set_location_assignment PIN_V3  -to ddr_dm[0]
set_location_assignment PIN_V8 -to ddr_dm[1]

#set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "ACTIVE SERIAL"
#set_global_assignment -name GENERATE_TTF_FILE ON
#set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "use as regular io"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "use as regular io"
set_global_assignment -name reserve_nws_nrs_ncs_cs_after_configuration "use as regular io"
set_global_assignment -name reserve_flash_nce_after_configuration "use as regular io"
set_global_assignment -name reserve_nceo_after_configuration "use as regular io"
set_global_assignment -name reserve_dclk_after_configuration "use as regular io"
set_global_assignment -name reserve_asdo_after_configuration "use as regular io"
#set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
#set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCS64
#set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
#set_global_assignment -name USE_CONFIGURATION_DEVICE OFF

set_instance_assignment -name OUTPUT_ENABLE_GROUP 1 -to ddr_dm
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1 -to ddr_dqs
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1 -to ddr_dq
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_rasb
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_casb
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_web
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_cke
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_ad[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_ad[1]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_ad[2]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_ad[3]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_ad[4]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_ad[5]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_ad[6]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_ad[7]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_ad[8]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_ad[9]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_ad[10]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_ad[11]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_ad[12]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_ba[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_ba[1]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_csb
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_dm[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_dm[1]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_dq[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_dq[1]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_dq[2]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_dq[3]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_dq[4]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_dq[5]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_dq[6]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_dq[7]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_dq[8]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_dq[9]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_dq[10]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_dq[11]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_dq[12]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_dq[13]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_dq[14]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_dq[15]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_dqs[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_dqs[1]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_clk #clk_to_sdram[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_clkn #clk_to_sdram_n[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ddr_rasb
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ddr_casb
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ddr_web
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ddr_cke
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ddr_ad[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ddr_ad[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ddr_ad[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ddr_ad[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ddr_ad[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ddr_ad[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ddr_ad[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ddr_ad[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ddr_ad[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ddr_ad[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ddr_ad[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ddr_ad[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ddr_ad[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ddr_ba[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ddr_ba[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ddr_csb
set_instance_assignment -name IO_STANDARD "2.5-V" -to clock_source
set_instance_assignment -name CUT ON -from ddr_dqs[0] -to *
set_instance_assignment -name CUT ON -from ddr_dqs[1] -to *
#set_location_assignment IOBANK_4 -to ddr_clk
#set_location_assignment IOBANK_4 -to ddr_clkn
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER ddr_clk -section_id ddr_sdram_clk_out_pair
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER ddr_clkn -section_id ddr_sdram_clk_out_pair
set_instance_assignment -name MAX_DATA_ARRIVAL_SKEW "100 ps" -from "ddrspa:\ddrsp0:ddrc0|ddr_phy:ddr_phy0|altera_ddr_phy:\alt:ddr_phy0|altpll:dll|_clk0" -to ddr_sdram_clk_out_pair
#set_instance_assignment -name MAX_DATA_ARRIVAL_SKEW "100 ps" -from "ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0" -to ddr_sdram_clk_out_pair
#set_instance_assignment -name TPD_REQUIREMENT "1.6 ns" -from *captured_* -to *resynched_data*
set_instance_assignment -name ADV_NETLIST_OPT_ALLOWED "NEVER ALLOW" -to "full_2s60:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io"
set_instance_assignment -name REMOVE_DUPLICATE_REGISTERS OFF -to "full_2s60:inst|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io"

set_instance_assignment -name CUT ON -from "clkgen:clkgen0|clkgen_cycloneiii:\cyc3:v|cyclone3_pll:sdclk_pll|altpll:\sden:altpll0|altpll_esv:auto_generated|clk[0]" -to "ddrspa:\ddrsp0:ddrc0|ddr_phy:ddr_phy0|ddrphy:ddr_phy0|cycloneiii_ddr_phy:\cyc3:ddr_phy0|apll:pll0|altpll:altpll_component|apll_altpll:auto_generated|wire_pll1_clk[0]"
set_instance_assignment -name CUT ON -from "ddrspa:\ddrsp0:ddrc0|ddr_phy:ddr_phy0|ddrphy:ddr_phy0|cycloneiii_ddr_phy:\cyc3:ddr_phy0|apll:pll0|altpll:altpll_component|apll_altpll:auto_generated|wire_pll1_clk[0]" -to "clkgen:clkgen0|clkgen_cycloneiii:\cyc3:v|cyclone3_pll:sdclk_pll|altpll:\sden:altpll0|altpll_esv:auto_generated|clk[0]"

set_global_assignment -name FMAX_REQUIREMENT "50.0 MHz"

#set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
#set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
#set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
#set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
#set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
#set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA

set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME ON
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF
set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"

set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to ddr_dm[0]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to ddr_dm[1]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to ddr_dq[0]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to ddr_dq[1]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to ddr_dq[2]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to ddr_dq[3]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to ddr_dq[4]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to ddr_dq[5]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to ddr_dq[6]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to ddr_dq[7]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to ddr_dq[8]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to ddr_dq[9]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to ddr_dq[10]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to ddr_dq[11]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to ddr_dq[12]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to ddr_dq[13]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to ddr_dq[14]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to ddr_dq[15]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to ddr_dqs[0]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to ddr_dqs[1]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_rasb
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_casb
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_web
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_cke
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_ad[0]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_ad[1]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_ad[2]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_ad[3]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_ad[4]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_ad[5]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_ad[6]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_ad[7]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_ad[8]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_ad[9]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_ad[10]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_ad[11]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_ad[12]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_ba[0]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_ba[1]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_csb
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_clk #clk_to_sdram[0]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to ddr_clkn #clk_to_sdram_n[0]
