=====================================================================
                         ARM-MvZbTˑ
                                  Last Modified: 2011 Jul 26 22:24:51
=====================================================================


(1) ΉĂ^[QbgVXe̎ށE\

ARM-Mˑ́CARMVx-MA[LeN`^[QbgƂĂDARMVx-ḾC
ARMƂ͈قȂCARM߂słȂ߁CARMˑƕĂD


(2) gpJƓ쌟؂io[WCIvVj

J[lGCCpăRpCDmFo[W͊e^[Q
bgˑ̃hLgɋLڂD


(3) ^[Qbg`̋K

(3-1) f[^^ɊւK

f[^^ arch/gcc/tool_stddef.h Œ`ĂeŁCfloat^
double^́CꂼIEEE754̒Px_Ɣ{x_
łD

(3-2) ݏɊւK

݃nhԍƊݔԍ̊āC҂̑Ή

݃nhԍƊݔԍ́COIPSRɃZbgO
pDSYSTICK15ԂŁCO݂16Ԃ̔ԍt
ĂD

ݗDx̒iKTMIN_INTPRI̒l

ݗDx̒iḰCSoCɃn[hEFAIɃT|[g銄ݗD
xrbgقȂ̂ŁC^[QbgˑɈقȂD^[Qbgˑ
́CݗDx̃rbgiTBITW_IPRIjƂ̊ݗDx̃TuD
x̃rbgiTBITW_SUBPRIj`D

erbg̒lCFG_INTŎgp\ȊݗDx͈͎̔͂̒ʂłD

   -(2^(TBIW_IPRI)) + (2^TBITW_SUBIPRI) ` -1

ႦΗDx̃rbg(TBITW_IPRI)8bitCTuDx̃rbg
(TBITW_SUBIPRI) 1bit̏ꍇ́C-254 ` -1 ͈̔͂łD

Dx̃rbg(TBITW_IPRI)3bitCTuDx̃rbg(TBITW_SUBIPRI) 
0bit̏ꍇ́C-8 ` -1 ͈̔͂łD

őDx(3bit̗ł-8)́CDxƂĂ"0x00"ƂȂD̗D
xCPUbNŗpBASEPRIWX^ł̓}XNłȂ߁CJ[l
݂̊̍ōDxiTMIN_INTPRIj́Cől1DxႢl
ȉ̒lw肷D

͈̔͂ŁCJ[lǗ݂̊̍ōDxiTMIN_INTPRIj^[Q
bgˑŐݒ肷D

dis_intena_int̃T|[g̗LC̐

dis_intena_intT|[gD͓ɂȂD

CFG_INT̐Ɗgi^[Qbg`Ŏgpł銄ݑj

CFG_INT̐͂ȂC^[Qbg`Ŏgp\Ȋݑ͓ɂ
D

J[lǗO̊

J[lǗO݂̊T|[gDw@́CݗDx̒iK
Ŏw肵CT|[g銄ݗDx̍ōliŏljC
TMIN_INTPRI̒l傫iDxႭjݒ肷ƁCTMIN_INTPRIl
iDxjȊݗDxݒ肵݂ݗDxƂĈD

J[lǗO݂̊OSs֎~ɂȂ邱Ƃ͂Ȃiɂ͊
̏ołZԋ֎~jCݔ́CJ[l̃R[ho
RɌĂяoD

J[lǗO݂̊ɑ΂CDEF_INH,CFG_INT̓T|[gD

(3-3) CPUOɊւK

CPUOnhԍ

CPUOnhԍƂẮCOIPSRɃZbgCOԍ
pDeO̗Oԍ͈ȉ̒ʂłD

        O              Oԍ
  Reset                      1
  Non-makable Interrupt      2
  Hard Fault                 3
  Memory Management          4
  Bus Fault                  5
  Usage Fault                6
  SVCall                    11
  Debug Monitor             12
  PendSV                    14

ȂCResetƁCSVCallɂẮCJ[lgp邽߁C[U[͎g
p邱ƂłȂD

ARM-MA[LeN`łCPUOɗDxݒ肷邱Ƃ\łD
ARM-Mˑł́CSĂCPUO̗DxCPUbNł̓}XNłȂ}
XNoȂliDx0jɏĂD

(3-4) CPUbNE݃bN

CPUbŃCbasepriTMIN_INTPRI̗Dx݂̊֎~lɐݒ肷
D݃bŃCFAULTMASK'1'ɐݒ肷邱ƂŎĂD

(3-5) \]pVXe̎QƂɊւK

get_utmT|[gDxɊւẮC^[QbgɈقȂD

(3-6) X^[gAbv[`ł̏e

X^[gAbv[`́CThread[hŌĂяo邱ƂOƂĂ
DsC݃bNԁiFAULTMASKZbgjƂD݃bN
Ԃ́CJ[l̏IɋDX^[gAbv[`ŁC
MSPANeBuȃX^bNƂCMSP̓e邽߂ɂ́CINIT_MSP
^[QbgˑŒ`D

(3-7) xN^e[uItZbg̏

vZbTˑ̏ŁCVector Table Offset Register ^[Qb
gˑ̏[`Őݒ肷DȂCxN^[e[úC.vector
̃ZNVtĂ邽߁CJXNvgł̃ZNV
w肵ĔzuD


(4) ^C}hCo֘Ȁ

J[l̃^CeBbNƂāCSYSTICgpꍇ́Ccore_config.c 
RpCΏۂƂCRtBM[Vt@C core_config.cfg 
w肷邱ƁD

̊{1msecƂDCALIBRATIONWX^̐ݒeɌvZ
ꍇ́CSYSTIC_USE_CALIBRATION `DCALIBRATIONWX^p
Ȃꍇ́C1msec̃JEgl TIMER_CLOCK ɐݒ肷DNb
N\[XƂāCONbNpꍇ́CSYSTIC_USE_STCLK pD


(5) ^[Qbgˑł̐ݒ荀

^[Qbgˑł͈ȉ̃}N`KvD

   TMAX_INTNO     : ݔԍ̍ől(ʏ̊ݔԍ + 15)
   TBITW_IPRI     : ݗDx̃rbg
   TBITW_SUBIPRI  : ݗDx̃rbg̃TuDx̃rbg
   TMIN_INTPRI    : ݗDx̍ŏliōlj
   TIC_NUME       : ^CeBbN̎̕q
   TIC_DENO       : ^CeBbN̎̕
   TIMER_CLOCK    : ^C}l̓\ƃ~bPʂƂ̕ϊ
   INTPRI_TIMER   : ^C}݊ݗDx
   INTATR_TIMER   : ^C}݂̊ݑ
   INIT_MSP       : X^[gAbv[`MSPꍇ͒`
   DEFAULT_ISTKSZ : X^bNTCYi8bytePʂŎwj
   SIL_DLY_TIM1   : ԑ҂̂߂̒`
   SIL_DLY_TIM2   : ԑ҂̂߂̒`


(6) ̑

(6-1) Configureation and Control Register(CCR)STKALIGN̐

VXeNimɂOS̏IjCCRSTKALIGN̐ݒ́C
XȂƁD


(7) fBNg\Et@C\
  ./arch/arm_m_gcc/common
    ./Makefile.core
    ./arm_m.h
    ./makeoffset.c
    ./core.tf
    ./core_cfg1_out.h
    ./core_check.tf
    ./core_config.c
    ./core_config.h
    ./core_def.csv
    ./core_insn.h
    ./core_kernel.h
    ./core_rename.def
    ./core_rename.h
    ./core_sil.h
    ./core_stddef.h
    ./core_support.S
    ./core_test.h
    ./core_timer.c
    ./core_timer.cfg
    ./core_timer.h
    ./core_unrename.h
    ./core_user.txt
    ./start.S


(8) o[W
2011/07/26
ECCRSTKALIGN'1'̏ꍇւ̑Ή
  ݁EȌoł́CX^bN͏8byteEƂȂ悤ɕ
  XD
  
2011/07/25
ECPUO̗Dx̏
  CPUbNŃ}XNłȂDxiDx0jɏ鏈ǉD
  
ECFG_INTŎgpł銄ݗDx̍ől̏C(core.tf)
  Eől1傫ȒlƂȂĂD
  
EJ[lǗO݂̊̈̕ύX
  Eʕł̈̕ύXɔύXD
  
E^C}݃nhłCOUNTFLAG̃NȀC
  SYSTIC_CONTROL_STATUSWX^COUNTFLAGNAɂ́C
  SYSTIC_CURRENT_VALUEWX^ǂݍޕKv邪C
  SYSTIC_CONTROL_STATUSWX^ǂݍłD

Ecore_int_entryɂbasepri̐ݒ
  NVICDx}XNIɐݒ肳邽ߗDx}XN̓_ł͕Kv
  Cx_get_ipm()basepriQƂ邽߁CbasepriXV悤ύXD
  

2011/07/24
E_ret_int_2/svc_handler ̕ύX
  ݗDx}XNSԂł^XNOĂяoȂ悤
  dlύXꂽ߁C_ret_int_2ł́CݗDx}XNCS
  ԁiTIPM_ENAALLjɐݒ肷悤ύXD
  svc_handler̓^XNɃ^[鎞basepriIIPM_ENAALLɂ悤
  ɕύXD
  
Ex_config_int()/set_exc_int_priority()̏C  
  x_config_int()Cset_exc_int_priority()ɑ΂ĊODx
  ČĂяo߁CDxŌĂяo悤CD
  set_exc_int_priority()󂯎DxƂėDxݒ
  悤ɏCD

2011/07/23
Eʕ1.4.0update.

EarmˑƓlɃ`bvˑu悤ɃfBNg\ύX

EarmˑƓlɃt@C̃vtBbNXcoreɕύXD

Ecall_atexit̍폜
  software_term_hook ̌ĂяóCcore_terminate()ɈړD
  
Eʕ1.7.0update.  

E^XNReLXgubŇ^̕ύX
  CTXB^TSKCTXB^ɖ̕ύXD

E^[QbgˑŃT|[g@\}N̕ύX
  TOPPERS_SUPPORT_DIS_INTTOPPERS_TARGET_SUPPORT_DIS_INTɁC
  TOPPERS_SUPPORT_ENA_INTTOPPERS_TARGET_SUPPORT_ENA_INTɁC
  ύXD
  
Eexc_sense_unlock̒`폜D  
  
EItZbgt@CRtBM[^Ő@ւ̑Ή

ECHECK_FUNC_ALIGNCCHECK_FUNC_NONNULLCCHECK_STACK_ALIGNC
  CHECK_STACK_NONNULLCCHECK_MPF_ALIGNCCHECK_MPF_NONNULL̒`C^
  [Qbgˑ̃ev[gt@CipX3jwb_t@CɈ
  D

E݂ƗO̖̓OύX
  int_entrycore_int_entryexc_entrycore_exc_entryɕύXD
  ItZbg̎擾@ύXƂȂ߁C̖Ô܂܂cfg1_out.c
  RpCG[ƂȂ邽߂ɕύXD
  
E^[QbgˑŒ`閼̂̃l[̒ǉ

Ecall_texrtnĂяoɁuipmflgtruevǉ
 
EJ[lǗOCPUÖ̕ύX


2011/07/22
Ex_disable_int() : prc_config.h ̏C   
 ݋֎~WX^̃AhX擾ۂɁCx[X̒luint32_t
 |C^ɃLXgĂȂ߁CAhXłĂ
 CD
 
E^XNReLXgp̃X^bN̏l}N(TOPPERS_ISTKPT)̏C 
  : prc_config.h
 oCgPʂŎ擾悤ɁC(char_t *) ɃLXgČfڂ悤ɏC
 D
  
ELOG_INH_ENTRYLOG_INH_LEAVĚL : prc_support.S
  LOG_INH_ENTRYLOG_INH_LEAVEłׂӏ LOG_EXC_ENTRY
  LOG_EXC_ENTRYɂȂĂCD

ETOPPERS_CUSTOM_IDLE typȍC : prc_support.S

Esvn_hanldeȑC :  prc_support.S
  ꗥEXC_FRAME_SIZẼX^bN̂ĂĂCConfigureation and 
  Control Register(CCR)STKALIGN'1'̏  ́C8byteEɃAC
  邽߁ĈĂTCYقȂDACꂽ́CxPSR9rb
  g`FbN邱Ƃɂ蔻肷D
  
Eprc.tf̏C
  boost̃o[Wɂĕς鋓zD
  http://www.toppers.jp/TOPPERS-USERS/201004/msg00034.html
  
E_kernel_istkpt ̍폜 : prc_cfg1_out.h
  _kernel_istkpt KvȂ^[Qbg݂邽߁CKvȂC^[Q
  bgˑŒ`悤ɕύXD

2008/08/22
Eprc_user.txt/prc_design.txt
  E2008/8/21̋Zpł̋c_ʂ𔽉fD
  
Eprc_support.S/prc_config.c/prc_config.h/arm_m.h
  EReLXgexc_ncntANeBuȃX^bNɕύX
  
Eprc_config.c
  Eset_exc_int_priority() ŃT|[g\IRQ̏239ɊgD
  
Estart.S 
  ENThread[hOƂĂ邱Ƃ𖾋LD
  Eu[g[_[Nꍇz肵CMSPLɂ悤
    ύXD
    
Eprc_timer.c
  ERgC
  EfobOpR[h폜

2008/07/11
Eŏ̃[X
