/* MANAGED-BY-SYSTEM-BUILDER                                    */
/* VisualDSP++ 5.0 Update 8                                     */
/* LDF Printer version: 5.8.0.3                                 */
/* ldfgen.exe version: 5.8.0.3                                  */
/* VDSG version: 5.8.0.3                                        */

/*
** ADSP-BF548 linker description file generated on Jun 09, 2010 at 22:41:24.
**
** Copyright (C) 2000-2010 Analog Devices Inc., All Rights Reserved.
**
** This file is generated automatically based upon the options selected
** in the LDF Wizard. Changes to the LDF configuration should be made by
** changing the appropriate options rather than editing this file.
**
** Configuration:-
**     crt_doj:                                BF548_EZKIT_POST_basiccrt.doj
**     processor:                              ADSP-BF548
**     product_name:                           VisualDSP++ 5.0 Update 8
**     si_revision:                            automatic
**     default_silicon_revision_from_archdef:  0.0
**     using_cplusplus:                        true
**     mem_init:                               false
**     use_vdk:                                false
**     use_eh:                                 true
**     use_argv:                               true
**     running_from_internal_memory:           true
**     user_heap_src_file:                     C:\Build_tools\ant_build\cvsStage\_5.0ExportBlackfinReGen\Examples\Blackfin\Examples\ADSP-BF548 EZ-KIT Lite\Power_On_Self_Test\BF548_EZKIT_POST_heaptab.c
**     libraries_use_stdlib:                   true
**     libraries_use_fileio_libs:              false
**     libraries_use_ieeefp_emulation_libs:    false
**     libraries_use_eh_enabled_libs:          false
**     system_heap:                            L1
**     system_heap_min_size:                   2k
**     system_stack:                           L1
**     system_stack_min_size:                  2k
**     use_sdram:                              false
**
*/

ARCHITECTURE(ADSP-BF548)

SEARCH_DIR($ADI_DSP/Blackfin/lib)


// Workarounds are enabled, exceptions are disabled.
#define RT_LIB_NAME(x) lib ## x ## y.dlb
#define RT_LIB_NAME_EH(x) lib ## x ## y.dlb
#define RT_LIB_NAME_MT(x) lib ## x ## y.dlb
#define RT_LIB_NAME_EH_MT(x) lib ## x ## y.dlb
#define RT_OBJ_NAME(x) x ## y.doj
#define RT_OBJ_NAME_MT(x) x ## mty.doj


$LIBRARIES = 

/*$VDSG<insert-user-libraries-at-beginning>                     */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-at-beginning>                     */

   RT_LIB_NAME_MT(small532)
   ,RT_LIB_NAME_MT(io532)
   ,RT_LIB_NAME_MT(c532)
   ,RT_LIB_NAME_MT(event532)
   ,RT_LIB_NAME(ssl548)
   ,RT_LIB_NAME(drv548)
   ,RT_LIB_NAME_MT(x532)
   ,RT_LIB_NAME_EH_MT(cpp532)
   ,RT_LIB_NAME_EH_MT(cpprt532)
   ,RT_LIB_NAME(f64ieee532)
   ,RT_LIB_NAME(dsp532)
   ,RT_LIB_NAME(sftflt532)
   ,RT_LIB_NAME(etsi532)
   ,RT_OBJ_NAME_MT(idle532)
   ,RT_LIB_NAME_MT(rt_fileio532)

/*$VDSG<insert-user-libraries-at-end>                           */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-at-end>                           */

   ;

$OBJECTS = 

/*$VDSG<insert-user-objects-at-beginning>                       */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-objects-at-beginning>                       */

     RT_LIB_NAME(profile532)
   , $COMMAND_LINE_OBJECTS
   , "cplbtab548.doj"

/*$VDSG<insert-user-objects-at-end>                             */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-objects-at-end>                             */

/*   , RT_OBJ_NAME(crtn548) */
   ;

$OBJS_LIBS_INTERNAL = 

/*$VDSG<insert-libraries-internal>                              */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-internal>                              */

   $OBJECTS{prefersMem("internal")}, $LIBRARIES{prefersMem("internal")}

/*$VDSG<insert-libraries-internal-end>                          */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-internal-end>                          */

   ;

$OBJS_LIBS_NOT_EXTERNAL = 

/*$VDSG<insert-libraries-not-external>                          */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-not-external>                          */

   $OBJECTS{!prefersMem("external")}, $LIBRARIES{!prefersMem("external")}

/*$VDSG<insert-libraries-not-external-end>                      */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-not-external-end>                      */

   ;

$OBJS_LIBS_WITH_AUTO_BREAKPOINTS = 

/*$VDSG<insert-libraries-with-auto-breakpoints>                 */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-with-auto-breakpoints>                 */

   $OBJECTS { FuncName("_main") ||
   FuncName("___lib_prog_term") ||
   FuncName("__primIO") ||
   FuncName("__ov_start") ||
   FuncName("__ov_end") ||
   FuncName("__dbg_assert") ||
   FuncName("__unknown_exception_occurred") ||
   FuncName("_cplb_init") ||
   FuncName("__KernelPanic") },
   $LIBRARIES { FuncName("_main") ||
   FuncName("___lib_prog_term") ||
   FuncName("__primIO") ||
   FuncName("__ov_start") ||
   FuncName("__ov_end") ||
   FuncName("__dbg_assert") ||
   FuncName("__unknown_exception_occurred") ||
   FuncName("_cplb_init") ||
   FuncName("__KernelPanic") }

/*$VDSG<insert-libraries-with-auto-breakpoints-end>             */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-with-auto-breakpoints-end>             */

   ;

$OBJS_LIBS_WITHOUT_AUTO_BREAKPOINTS = 

/*$VDSG<insert-libraries-without-auto-breakpoints>              */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-without-auto-breakpoints>              */

   $OBJECTS { !FuncName("_main") &&
   !FuncName("___lib_prog_term") &&
   !FuncName("__primIO") &&
   !FuncName("__ov_start") &&
   !FuncName("__ov_end") &&
   !FuncName("__dbg_assert") &&
   !FuncName("__unknown_exception_occurred") &&
   !FuncName("_cplb_init") &&
   !FuncName("__KernelPanic") },
   $LIBRARIES { !FuncName("_main") &&
   !FuncName("___lib_prog_term") &&
   !FuncName("__primIO") &&
   !FuncName("__ov_start") &&
   !FuncName("__ov_end") &&
   !FuncName("__dbg_assert") &&
   !FuncName("__unknown_exception_occurred") &&
   !FuncName("_cplb_init") &&
   !FuncName("__KernelPanic") }

/*$VDSG<insert-libraries-without-auto-breakpoints-end>          */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-without-auto-breakpoints-end>          */

   ;


/*$VDSG<insert-user-macros>                                     */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-macros>                                     */


/*$VDSG<customize-async-macros>                                 */
/* This code is preserved if the LDF is re-generated.           */


#define ASYNC0_MEMTYPE RAM
#define ASYNC1_MEMTYPE RAM
#define ASYNC2_MEMTYPE RAM
#define ASYNC3_MEMTYPE RAM


/*$VDSG<customize-async-macros>                                 */


/*
** Memory map.
**
** 0xFFE00000 - 0xFFFFFFFF  Core MMR registers (2MB)
** 0xFFC00000 - 0xFFDFFFFF  System MMR registers (2MB)
** 0xFFB01000 - 0xFFBFFFFF  Reserved
** 0xFFB00000 - 0xFFB00FFF  Scratch SRAM (4K)
** 0xFFA24000 - 0xFFAFFFFF  Reserved
** 0xFFA14000 - 0xFFA23FFF  L1 ROM (64k)
** 0xFFA10000 - 0XFFA13FFF  Code SRAM/CACHE (16K)
** 0xFFA0C000 - 0xFFA0FFFF  Reserved
** 0xFFA08000 - 0xFFA0BFFF  Instruction Bank B SRAM (16K)
** 0xFFA00000 - 0xFFA07FFF  Instruction Bank A SRAM (32K)
** 0xFF908000 - 0xFF9FFFFF  Reserved
** 0xFF904000 - 0xFF907FFF  Data Bank B SRAM/CACHE (16k)
** 0xFF900000 - 0XFF903FFF  Data Bank B SRAM (16k)
** 0xFF808000 - 0xFF8FFFFF  Reserved
** 0xFF804000 - 0xFF807FFF  Data Bank A SRAM/CACHE (16k)
** 0xFF800000 - 0XFF803FFF  Data Bank A SRAM (16k)
** 0xFEB20000 - 0xFF7FFFFF  Reserved
** 0xFEB00000 - 0xFEB1FFFF  L2 SRAM (128K)
** 0xEF001000 - 0xFFAFFFFF  Reserved
** 0xEF000000 - 0xFF8007FF  Boot ROM (2K)
** 0x30000000 - 0xEEFFFFFF  Reserved
** 0x2C000000 - 0x2FFFFFFF  ASYNC MEMORY BANK 3 (64MB)
** 0x28000000 - 0x2BFFFFFF  ASYNC MEMORY BANK 2 (64MB)
** 0x24000000 - 0x27FFFFFF  ASYNC MEMORY BANK 1 (64MB)
** 0x20000000 - 0x23FFFFFF  ASYNC MEMORY BANK 0 (64MB)
**            - 0x1FFFFFFF  DDR1 MEM Bank 1 MEMORY (8MB - 256MB)
** 0x00000000               DDR1 MEM Bank 0 MEMORY (8MB - 256MB)
** 
** Notes:
** 0xFF807FEF-0xFF807FFF Required by boot-loader.
*/

MEMORY
{

   MEM_L1_SCRATCH       { START(0xFFB00000) END(0xFFB00FFF) TYPE(RAM) WIDTH(8) }
   MEM_L1_CODE_CACHE    { START(0xFFA10000) END(0xFFA13FFF) TYPE(RAM) WIDTH(8) }
   MEM_L1_CODE          { START(0xFFA00000) END(0xFFA0BFFF) TYPE(RAM) WIDTH(8) }

/*   MEM_L1_DATA_B_CACHE  { START(0xFF904000) END(0xFF907FFF) TYPE(RAM) WIDTH(8) } */
   MEM_L1_DATA_B        { START(0xFF900000) END(0xFF903FFF) TYPE(RAM) WIDTH(8) }

/*   MEM_L1_DATA_A_CACHE  { START(0xFF804000) END(0xFF807FFF) TYPE(RAM) WIDTH(8) } */
   MEM_L1_DATA_A        { START(0xFF800000) END(0xFF807FFF) TYPE(RAM) WIDTH(8) }

   MEM_L2_SRAM          { START(0xFEB00000) END(0xFEB1FFFF) TYPE(RAM) WIDTH(8) }

   MEM_ASYNC3           { START(0x2C000000) END(0x2FFFFFFF) TYPE(RAM) WIDTH(8) }
   MEM_ASYNC2           { START(0x28000000) END(0x2BFFFFFF) TYPE(RAM) WIDTH(8) }
   MEM_ASYNC1           { START(0x24000000) END(0x27FFFFFF) TYPE(RAM) WIDTH(8) }
   MEM_ASYNC0           { START(0x20000000) END(0x23FFFFFF) TYPE(RAM) WIDTH(8) }
    /* 
    ** The EBIU allows for 4 sub-banks to be accessed simultaneously
    ** The LDF partitions the available SDRAM into 4 16MB banks which makes
    ** the best use of the EBIU and minimizes memory access stall cycles.
    ** bank0-heap, bank1-data, bank2-data/bsz, bank3-program
    ** See theparts  Hardware Reference Manual, SDRAM controller section
    ** for further information.
    */
   MEM_SDRAM0_BANK0     { START(0x00000004) END(0x00FFFFFF) TYPE(RAM) WIDTH(8) }
   MEM_SDRAM0_BANK1     { START(0x01000000) END(0x01FFFFFF) TYPE(RAM) WIDTH(8) }
   MEM_SDRAM0_BANK2     { START(0x02000000) END(0x02FFFFFF) TYPE(RAM) WIDTH(8) }
   MEM_SDRAM0_BANK3     { START(0x03000000) END(0x03FFFFFF) TYPE(RAM) WIDTH(8) }

} /* MEMORY */

PROCESSOR p0
{
   OUTPUT($COMMAND_LINE_OUTPUT_FILE)
   RESOLVE(start, 0xFFA00000)
   RESOLVE(___argv_string, 0xFF800000)
   KEEP(start, _main)
   
   /*$VDSG<insert-user-ldf-commands>                            */
   /* Text inserted between these $VDSG comments will be preserved */
   /*$VDSG<insert-user-ldf-commands>                            */
   
   SECTIONS
   {
      /* Workaround for hardware errata 05-00-0189 and 05-00-0310 -
      ** "Speculative (and fetches made at boundary of reserved memory
      ** space) for instruction or data fetches may cause false
      ** protection exceptions" and "False hardware errors caused by
      ** fetches at the boundary of reserved memory ".
      **
      ** Done by avoiding use of 76 bytes from at the end of blocks
      ** that are adjacent to reserved memory. Workaround is enabled
      ** for appropriate silicon revisions (-si-revision switch).
      */
      RESERVE(___wab0=MEMORY_END(MEM_L1_SCRATCH) - 75, ___l0 = 76)
      RESERVE(___wab1=MEMORY_END(MEM_L1_CODE_CACHE) - 75, ___l1 = 76)
      RESERVE(___wab2=MEMORY_END(MEM_L1_CODE) - 75, ___l2 = 76)
/*      RESERVE(___wab3=MEMORY_END(MEM_L1_DATA_B_CACHE) - 75, ___l3 = 76) */
      RESERVE(___wab4=MEMORY_END(MEM_L1_DATA_B) - 75, ___l4 = 76)
/*      RESERVE(___wab5=MEMORY_END(MEM_L1_DATA_A_CACHE) - 75, ___l5 = 76) */
      RESERVE(___wab6=MEMORY_END(MEM_L1_DATA_A) - 75, ___l6 = 76)
      RESERVE(___wab7=MEMORY_END(MEM_L2_SRAM) - 75, ___l7 = 76)
      RESERVE(___wab8=MEMORY_END(MEM_ASYNC3) - 75, ___l8 = 76)
      RESERVE(___wab9=MEMORY_END(MEM_SDRAM0_BANK3) - 75, ___l9 = 76)
      
      /*$VDSG<insert-new-sections-at-the-start>                 */
      /* Text inserted between these $VDSG comments will be preserved */
      /*$VDSG<insert-new-sections-at-the-start>                 */
      
      scratchpad NO_INIT
      {
         INPUT_SECTION_ALIGN(4)
         
         /*$VDSG<insert-input-sections-at-the-start-of-scratchpad>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-scratchpad>  */
         
         INPUT_SECTIONS($OBJECTS(L1_scratchpad) $LIBRARIES(L1_scratchpad))
         
         /*$VDSG<insert-input-sections-at-the-end-of-scratchpad>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-scratchpad>  */
         
      } > MEM_L1_SCRATCH
      
      L1_code
      {
         INPUT_SECTION_ALIGN(4)
         ___l1_code_cache = 0;
         INPUT_SECTIONS($OBJS_LIBS_WITH_AUTO_BREAKPOINTS(program))
         INPUT_SECTIONS($OBJECTS(L1_code) $LIBRARIES(L1_code))
         
         /*$VDSG<insert-input-sections-at-the-start-of-l1_code>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-l1_code>  */
         
         INPUT_SECTIONS($OBJECTS(cplb_code) $LIBRARIES(cplb_code))
         INPUT_SECTIONS($OBJECTS(cplb) $LIBRARIES(cplb))
         INPUT_SECTIONS($OBJECTS(noncache_code) $LIBRARIES(noncache_code))
         INPUT_SECTIONS($OBJS_LIBS_INTERNAL(program))
         INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(program))
         INPUT_SECTIONS($OBJECTS(program) $LIBRARIES(program))
         
         /*$VDSG<insert-input-sections-at-the-end-of-l1_code>   */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-l1_code>   */
         
      } > MEM_L1_CODE
      
      L1_data_a_tables
      {
         INPUT_SECTION_ALIGN(4)
         FORCE_CONTIGUITY
         
         /*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_tables>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_tables>  */
         
         INPUT_SECTIONS($OBJECTS(ctor) $LIBRARIES(ctor))
         INPUT_SECTIONS($OBJECTS(ctorl) $LIBRARIES(ctorl))
         INPUT_SECTIONS($OBJECTS(.gdt) $LIBRARIES(.gdt))
         INPUT_SECTIONS($OBJECTS(.gdtl) $LIBRARIES(.gdtl))
         
         /*$VDSG<insert-input-sections-at-the-end-of-L1_data_a_tables>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-L1_data_a_tables>  */
         
      } > MEM_L1_DATA_A
      
      L1_data_a_1
      {
         INPUT_SECTION_ALIGN(4)
         ___l1_data_cache_a = 0;
         INPUT_SECTIONS($OBJECTS(L1_data_a) $LIBRARIES(L1_data_a))
         INPUT_SECTIONS($OBJECTS(L1_data) $LIBRARIES(L1_data))
         
         /*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_1>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_1>  */
         
         RESERVE(heaps_and_stack_in_L1_data_a, heaps_and_stack_in_L1_data_a_length = 4096,4)
      } > MEM_L1_DATA_A
      
      L1_data_a_bsz ZERO_INIT
      {
         INPUT_SECTION_ALIGN(4)
         
         /*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_bsz>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_bsz>  */
         
         INPUT_SECTIONS( $OBJECTS(L1_bsz) $LIBRARIES(L1_bsz))
         
         /*$VDSG<insert-input-sections-at-the-end-of-L1_data_a_bsz>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-L1_data_a_bsz>  */
         
      } > MEM_L1_DATA_A
      
      bsz_L1_data_a ZERO_INIT
      {
         INPUT_SECTION_ALIGN(4)
         
         /*$VDSG<insert-input-sections-at-the-start-of-bsz_L1_data_a>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-bsz_L1_data_a>  */
         
         INPUT_SECTIONS($OBJS_LIBS_INTERNAL(bsz))
         INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(bsz))
         INPUT_SECTIONS($OBJECTS(bsz) $LIBRARIES(bsz))
         
         /*$VDSG<insert-input-sections-at-the-end-of-bsz_L1_data_a>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-bsz_L1_data_a>  */
         
      } > MEM_L1_DATA_A
      
      L1_data_a
      {
         INPUT_SECTION_ALIGN(4)
         
         /*$VDSG<insert-input-sections-at-the-start-of-L1_data_a>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-L1_data_a>  */
         
         INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata))
         INPUT_SECTIONS($OBJS_LIBS_INTERNAL(data1))
         INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(data1))
         INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1))
         INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata))
         INPUT_SECTIONS($OBJECTS(cplb_data) $LIBRARIES(cplb_data))
         
         /*$VDSG<insert-input-sections-at-the-end-of-L1_data_a>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-L1_data_a>  */
         
      } > MEM_L1_DATA_A
      
      L1_data_a_2
      {
         INPUT_SECTION_ALIGN(4)
         
         /*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_2>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_2>  */
         
         INPUT_SECTIONS($OBJECTS(vtbl) $LIBRARIES(vtbl))
         INPUT_SECTIONS($OBJECTS(.frt) $LIBRARIES(.frt))
         INPUT_SECTIONS($OBJECTS(.rtti) $LIBRARIES(.rtti))
         INPUT_SECTIONS($OBJECTS(.edt) $LIBRARIES(.edt))
         INPUT_SECTIONS($OBJECTS(.cht) $LIBRARIES(.cht))
         
         /*$VDSG<insert-input-sections-at-the-end-of-L1_data_a_2>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-L1_data_a_2>  */
         
      } > MEM_L1_DATA_A
      
      L1_data_a_stack_heap
      {
         INPUT_SECTION_ALIGN(4)
         RESERVE_EXPAND(heaps_and_stack_in_L1_data_a, heaps_and_stack_in_L1_data_a_length , 0, 4)
         ldf_stack_space = heaps_and_stack_in_L1_data_a;
         ldf_stack_end = (ldf_stack_space + (((heaps_and_stack_in_L1_data_a_length * 2048) / 4096) - 4)) & 0xfffffffc;
         ldf_heap_space = ldf_stack_end + 4;
         ldf_heap_end = (ldf_heap_space + (((heaps_and_stack_in_L1_data_a_length * 2048) / 4096) - 4)) & 0xfffffffc;
         ldf_heap_length = ldf_heap_end - ldf_heap_space;
      } > MEM_L1_DATA_A
      
      /*$VDSG<insert-new-sections-at-the-end>                   */
      /* Text inserted between these $VDSG comments will be preserved */
      /*$VDSG<insert-new-sections-at-the-end>                   */
      
   } /* SECTIONS */
} /* p0 */

